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The rapid miniaturization of electronics to the submicrometer scale has led to remarkable increases in computing power while enabling reductions in...



= Encyclopedia Article; = Research Update
Figure 1.Scanning electron microscopy image of as-synthesized semiconductor nanowires. The insets show higher-resolution transmission electron microscopy images of the nanowires.
From update 'Nanowire nanocircuits'
Figure 2.Assembly of nanowires. (a) Parallel-nanowire arrays obtained by passing a nanowire solution through a channel on a substrate. (b) Crossed-nanowire matrix obtained by rotating the flow direction 90° in a sequential flow alignment step.
From update 'Nanowire nanocircuits'
Figure 3.Crossed-nanowire devices. (a) Current-voltage (I-V) data for crossed-nanowire pn diodes. (b) I-V behavior for a 4(p) × 1(n) multiple junction array. (c) Schematics of the crossed-nanowire FET concept. (d) Gate-dependent I-V characteristics of a crossed-nanowire FET formed using a p-type nanowire as the conducting channel and an n-type nanowire as the local gate. The curves in the inset show Isd vs. Vgate for n-type nanowire (lower curve) and global back (upper curve) gates when Vsd is set at 1 volt. The FET conductance modulation is much more significant with the nanowire gate (>105) than with a back gate (<10).
From update 'Nanowire nanocircuits'